The present invention relates to circuits and, more particularly, to error correcting circuits.
NAND-type flash memory may include memory cells connected in series between a drain selection transistor and a source selection transistor. The number of memory cells may vary with devices or density.
In the NAND-type flash memory, the channel voltage of a programmed cell may be nearly 0 V while the channel voltage of an erased cell may be boosted up to about 9 V. However, the channel voltage may not satisfactorily increase due to a parasitic capacitor generated between channels of the two cells, which may cause program disturbance. Moreover, a coupling effect may occur between cells adjacent in a bit line direction due to a parasitic capacitor, and therefore, the threshold voltage of a memory cell intervened between two cells adjacent in the bit line direction may increase.
Each possible program states of a memory cell may have a fixed threshold voltage distribution, and therefore, when the threshold voltage distribution shifts due an external environment factor, a likelihood of error occurrence may increase during a data read operation.